EVAL-AD1870EB【PDF 13/20 页】Single-Supply 16-Bit Stereo ADC

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AD1870

REV. A

–

Timing Parameters

For master modes, a BCLK transmitting edge (labeled

“

XMIT

”

)

will be delayed from a CLKIN rising edge by t

DLYCKB

, as shown

in Figure 17. A L

CK transition will be delayed from a BCLK

transmitting edge by t

DLYBLR

. A WCLK rising edge will be

delayed from a BCLK transmitting edge by t

DLYBWR

, and a WCLK

falling edge will be delayed from a BCLK transmitting edge by

DLYBWF

. The DATA and TAG outputs will be delayed from a

transmitting edge of BCLK by t

DLYDT

For slave modes, an L

CK transition must be set up to a BCLK

sampling edge (labeled

“

SAMPLE

”

) by t

SETLRBS

(see Figure 18).

The DATA and TAG outputs will be delayed from an L

transition by t

DLYLRDT

, and DATA and TAG outputs will be

delayed from BCLK transmitting edge by t

DLYBDT

. For Slave

Mode, Data Position Controlled by WCLK Input, WCLK must

be set up to a BCLK sampling edge by t

SETWBS

For both Master and Slave Modes, BCLK must have a mini-

mum LO pulsewidth of t

BPWL

and a minimum HI pulsewidth of

BPWH

The AD1870 CLKIN and

RESET

timing is shown in Figure 19.

CLKIN must have a minimum LO pulsewidth of t

CPWL

and a

minimum HI pulsewidth of t

CPWH

. The minimum period of

CLKIN is given by t

CLKIN

RESET

must have a minimum LO

pulsewidth of t

RPWL

. Note that there are no setup or hold time

requirements for

RESET

Master Clock (CLKIN) Considerations

It is recommended that the BCLK and L

CK are derived from

CLKIN to ensure correct phase relationships. The modulator

of the AD1870 runs at 64

. Therefore, best performance is

obtained when the BCLK rate equals 64

or 32

. BCLK

rates such as 48

may result in an increased spectral noise

floor, depending on the phase relationship of BCLK to CLKIN.

Synchronizing Multiple AD1870s

Multiple AD1870s can be synchronized by making all the

AD1870s serial port slaves. This option is illustrated in Figure 6.

See the Reset, Autocalibration, and Power-Down section for

additional information.

#1 AD1870

SLAVE MODE

CLKIN

DATA

BCLK

WCLK

CLOCK

SOURCE

#2 AD1870

SLAVE MODE

CLKIN

DATA

BCLK

WCLK

#N AD1870

SLAVE MODE

CLKIN

DATA

BCLK

WCLK

RESET

Figure 6. Synchronizing Multiple AD1870s

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